Recent emphasis in radio receiver/modem technology research has focused on the utilization of digital signal processing to demodulate signals. Communication using digital modulation techniques requires that the receiver be able to accurately identify the symbol timing epoch, i.e., the optimum sampling point on a waveform for symbol detection. Presently, symbol synchronization is generally derived from an analog signal using analog and/or digital circuits. That is, symbol synchronizer implementations typically use a continuous-time data signal to derive a symbol clock. Even so-called digital synchronizer structures and commercially available digital phase-locked loops process continuous-time rather than sampled, or discrete-time, signals to derive the symbol timing reference. However, the aforementioned recent interest in digital, i.e. sampled, demodulation techniques has made it desirable to provide symbol synchronizers that derive the required symbol clock reference from a discrete-time, rather than continuous-time, signal. To be practicable, such a symbol synchronizer should provide a stable symbol clock reference even under noisy or lengthy transmission conditions. Furthermore, it is desirable that such symbol synchronizer structures be capable of being implemented using either VLSI technology or microprocessor code.